1. Field of the Invention
The present invention relates to a demodulation circuit for demodulating modulated continuous binary signals and a camera with the demodulation circuit.
2. Related Background Art
The invention associated with a technique of this type, U.S. Pat. No. 4,964,139 is known, and has an arrangement shown in FIG. 10 and timing characteristics shown in FIG. 11.
A binary information decoder circuit 100 shown in FIG. 10 comprises a read/write magnetic head 101, a pre-amplifier 102 for amplifying the output signal from the magnetic head, a filter 103 for removing an unnecessary component from the amplified output, a post-amplifier 104 for amplifying the output signal from the filter 103, a detector 105 (including a negative peak detector (NPD) 106 and a positive peak detector (PPD) 107) for detecting necessary signal components from the output signal from the post-amplifier 104, a delay circuit 108 connected to the NPD 106, a flip-flop circuit 109, which is set in response to the output from the delay circuit 108, and is cleared in response to the output from the PPD 107, a clock circuit 110 for generating a clock signal, and an up/down counter 111 for counting up/down the output from the flip-flop circuit 109.
The most significant bit (MSB) of the output from the up/down counter 111 and the output (CLOCK) from the NPD 106 are supplied to a computer 112.
In this circuit, as shown in FIG. 11, a pulse read signal (B) from the magnetic head 101 appears in synchronism with the leading and trailing edges of a modulated data waveform (A), and corresponding threshold peaks (C) of the read signal (B) are detected by the NPD 106 and the PPD 107. The flip-flop circuit 109 is driven by the outputs (D) from the NPD 106 and the PPD 107.
Modulation in this case is made such that when a data signal rises before a time 1/2 the interval of the clock signal (C) (left side of FIG. 11), it indicates "0"; when the data signal rises after the time (right side of FIG. 11), it indicates "1".
However, according to this prior art, since a count-down operation continues even after an overflow signal is output in a count-down mode, the overflow signal (MSB=1) becomes MSB=0, and a signal to be demodulated to "0" is undesirably demodulated to "1".
When the clock interval (C) in FIG. 11 becomes larger than the count value of the counter 111, an overflow signal (MSB=1) is undesirably output even in a count-up mode, and a signal to be demodulated to "1" is undesirably demodulated to "0".